SoC Architecture Explorer
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چکیده
SoC Architecture Explorer is an architecture exploration tool for SoC design. It explores all possible parameter sets under constraints and estimates design quality of every architecture candidates.
منابع مشابه
Embedded Memory Test Strategies and Repair
The demand of self-testing proportionally increases with memory size in System on Chip (SoC). SoC architecture normally occupies the majority of its area by memories. Due to increase in density of embedded memories, there is a need of self-testing mechanism in SoC design. Therefore, this research study focuses on this problem and introduces a smooth solution for self-testing. In the proposed m...
متن کاملLOW-POWER SYSTEMS-ON-CHIP Bus encoding architecture for low-power implementation of an AMBA-based SoC platform
Advanced microcontroller bus architecture (AMBA) is rapidly becoming the de facto standard for new system-on-chip (SoC) designs. The bus protocol is complex, making any peripherals that can interface to it valuable intellectual property (IP). This paper presents a lowpower bus encoding architecture which is able to deal with the complex advanced highperformance bus (AHB) protocol within AMBA, w...
متن کاملFPGA Implementation of JPEG and JPEG2000-Based Dynamic Partial Reconfiguration on SOC for Remote Sensing Satellite On-Board Processing
This paper presents the design procedure and implementation results of a proposed hardware which performs different satellite Image compressions using FPGA Xilinx board. First, the method is described and then VHDL code is written and synthesized by ISE software of Xilinx Company. The results show that it is easy and useful to design, develop and implement the hardware image compressor using ne...
متن کاملError Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs
This work-in-progress paper surveys error detection techniques for transient, timing, permanent and logical errors in system-on-chip (SoC) design and discusses their applicability in the design of monitors for our Autonomic SoC architecture framework. These monitors will be needed to deliver necessary signals to achieve fault-tolerance, self-healing and self-calibration in our Autonomic SoC arc...
متن کاملQNoC: QoS architecture and design process for network on chip
We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design process. SoC inter-module communication traffic is classified into four classes of service: signaling (for inter-module control signals); real-time (representing delay-constrained bit streams); RD/WR (modeling short data access) and bloc...
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